XSCC-0001 User Manual

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Performance
~2.9 MHz (2.9 million operations per second)
(NOTE: this was measured by doing MOV operations, the speed might be higher or lower depending on your device and operations used.)
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Cache
The XSCC-0001 has 512 bytes/items of cache. (Cache is not RAM and cannot handle pointers like it can.)
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Registers
• 1: rax
• 2: rbx
• 3: rcx
• 4: rdx
–
• 5: eax
• 6: ebx
• 7: ecx
• 8: edx
–
• 9: dx
• 10: dy
• 11: dz
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Pins
1: Clock Signal (Set to 1 to execute the next instruction. XSCC-0001 resets it to 0 after execution.)
–
2: Flash Signal (Set to 1 to flash the machine code provided on Pin 3.)
–
3: Flash Data (Provides the raw XSCC-0001 machine code to be flashed into the processor.)
–
4-40: General purpose I/O (Can be used for anything.)
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Opcodes
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<0x00> | MOV reg val –
<0x01> | ADD reg reg –
<0x02> | SUB reg reg –
<0x03> | MUL reg reg –
<0x04> | DIV reg reg – (only does integer division.)
<0x05> | JMP addr – –
<0x06> | CMP Reg1 operation Reg2 (compares Reg1 to Reg2 Operation Numbers:(1:== 2:!= 3:> 4:< 5:<= 6:>=))
<0x07> | CJMP addr – –
<0x08> | OUT reg pin –
<0x09> | IN reg pin –
<0x0a> | PUSH1 reg – –
<0x0b> | POP1 reg – –
<0x0c> | PUSH2 reg – –
<0x0d> | POP2 reg – –
<0x0e> | PUSH3 reg – –
<0x0f> | POP3 reg – –
<0x10> | CALL addr – –
<0x11> | RET – – –
<0x12> | MOD reg reg –
<0x13> | COPY src_reg dest_reg – (copies the value of src_reg to dest_reg)
<0x14> | HALT – – –
<0x15> | STOR reg cache_addr – (think: “STORE register at cache_addr”)
<0x16> | LOAD reg cache_addr – (think: “LOAD register from cache_addr”)
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ROM Format
(1 + 1 example)
Padded
Non-Padded
(Spaces are mandatory)
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Official Models
XSCC-0001
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Official Compilers
(Compatibility means how well it works with this XSCC model.)
• XASM (100% compatible)
• XCL (75% compatible)
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Fan-Made Compilers
ERROR 404: Compilers not found. (Maybe you could change that?)
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Fan-Made Models
ERROR 404: Models not found. (Maybe you could change that?)

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